With rising mission critical application and competition, inserting testing capability in the design stage of the chip is ever so important. Our team have expertise in developing and integrating a complete test strategy for your ASIC design to deliver high fault coverage. DFT techniques that can be applied to your design include:
- Scan Insertion
- ATPG
- FPGA-to-FPGA, FPGA-to-ASIC, ASIC-to-FPGA conversion
- Test pattern generation and simulation
- Coverage improvement
- IDDQ
- BIST
- BSCAN
- DFT Spyglass checks
- Test mode timing constraints