We provide support throughout RTL to GDSII stages of ASIC development flow. Our experienced team has developed advanced flows for power aware synthesis (UPF, CPF), timing constraint generation (STA), netlist floor planning for best possible PPA and place and route(PNR) for overcoming ever increasing complexity. Our engineers in-depth knowledge of EDA tools and scripting skills enable us to deliver full turn-key ASIC development.
- Synthesis
- STA
- Floor planning
- Place & Route
- Low Power Implementation
- Crosstalk Analysis
- All Signoff Checks (PV, STA, IR/EM, LEC etc)
- ICC2, Innovus, Calibre, RC, DC, RedHawk, PT/PTSI
